Electrically conductive lines form many common components of integrated circuits. Dynamic random access memory (DRAM) circuitry, for example, incorporates multiple parallel conductive lines to form wordlines and bitlines. In order to increase capacity and accommodate smaller devices, there is constant pressure to increase the density of components on these and other circuits. The continual reduction in feature sizes places greater demands on the techniques used to form the features.
Photolithography is a commonly used technique for patterning integrated circuit features. One example of a photolithographic method for forming conductive lines using conventional photolithographic techniques is illustrated in FIGS. 1A through 1D. FIG. 1A shows a substrate 11, such as a semiconductor substrate or an insulating material substrate. For forming word lines on a semiconductor substrate 11, materials are sequentially deposited over a semiconductor substrate 11, including a gate oxide material 31, a polysilicon material 35, a metal silicide material 37, and an oxide top material 41. The last set of materials deposited comprise a photo patterning stack, which may include photoresist anti-reflective coatings and hardmask materials. Any photoresist materials 33 may be used for the photo patterning stack, including positive photoresist materials (such as DNQ-Novolac) and negative photoresist materials (such as SU-8). In this example, a negative photoresist is used, so that when the photoresist material 33 is exposed to light through a mask (at portions 60, 61) and developed, the area that has not been exposed to light is dissolved.
FIG. 1B shows the remaining photoresist material 33 after unexposed portions of the material have been removed. The remaining photoresist material 33 is used as an etch mask for an etching process. In the etching process, portions of the of the gate oxide 31, polysilicon 35, metal silicide 37 and oxide top material 41 that are not covered by the photoresist material 31 are removed by, for example, wet or dry chemical etch. After the etch, the remaining photoresist material 33 is dissolved. FIG. 1C illustrates a cross sectional view of the resulting stack. Once the desired layers have been patterned, an encapsulation insulating material 51 can be deposited and etched. Any suitable insulating material 51, such as an oxide, may be used. FIG. 1D shows an insulating material 51 that has been deposited over the materials and etched from the substrate 11. The encapsulation covers the top and both sides of the underlying materials 31, 35, 37, and 41. Other known techniques for forming an encapsulation insulating material 51 over the materials 31, 35, 37 and 41 can also be used.
There are limitations on how close line features, such as conductive lines, can be patterned using such known photolithographic techniques. The size of line features on an integrated circuit are conventionally described by their “pitch,” which is the distance between an identical point on two neighboring features. Features are typically defined by spaces between adjacent features, and so the pitch can be viewed as the sum of the width of a line feature (x in FIG. 1D) and the width of the space separating that line feature from a neighboring line feature (y in FIG. 1D). The “half pitch” is half the sum of the feature width x and the width y of the space between features. Due to factors such as optics and light or radiation wavelength, there is a minimum pitch below which line features cannot be reliably formed using conventional photolithographic techniques. Conventional photolithographic techniques, one example of which is illustrated in FIGS. 1A-1D, can form parallel spaced conductive lines with a half pitch as low as about 45 nm. More advanced photolithographic techniques, such as double patterning and spacer pitch doubling, enable the formation of conductive lines with a half pitch as low as about 20 nm. Examples of these techniques can be found in U.S. Pat. No. 5,378,649 to Huang (double-patterning), and U.S. Pat. No. 5,328,810 to Lowrey et al. (spacer pitch doubling).
Recently developed non-lithographic techniques, such as polymer self assembly, have also made it possible to form parallel conductive lines with even smaller spacing between adjacent lines. For example, using block copolymer (BCP) self assembly, conductive lines with a half pitch below 20 nm are achievable. FIGS. 2A and 2B illustrate patterns formed using BCP self assembly techniques. The process of forming self-assembled patterns involves the deposition of a thin BCP film composed of, for example, polystyrene (PS) and polymethylmethacrylate (PMMA) (referred to as PS-b-PMMA). This is followed by thermal annealing above the glass transition temperature of the BCP. The quality of the resulting pattern depends on process conditions including film thickness, annealing time, and annealing temperature. FIG. 2A illustrates BCP cylinders 80 (comprising, for example, PS) formed in a matrix phase material 82 (comprising, for example PMMA). Notice that the cylinders do not naturally align in a symmetrical pattern. Various methods can be employed in order to control the orientation of the cylinders, including the use of external thermal or electric fields, shear stress or flow, chemical nanopatterning, or graphoepitaxy. FIG. 2B illustrates parallel spaced copolymer cylinders 80 formed using a graphoepitaxy technique, wherein surface relief (in the form of trenches 84) is used to induce orientation.
Once formed, the BCP cylinders 80 can be used as a sacrificial template for patterning underlying materials, similar to the way photoresist material is used in conventional photolithographic methods. To accomplish this, the PMMA material is chemically removed by exposure to UV light and immersion in a developer, such as an acetic acid developer. The remaining PS cylinders can then be used as a mask to etch underlying materials, such as a conductive material or (more typically) a hardmask. BCP cylinders 80 can also be metalized to function as conductive lines. BCP cylinders 80 can be metalized by, for example, soaking the cylinders in an acidic metal salt solution. For more information on BCP self assembly techniques, see C. T. Black, et al., Polymer Self Assembly in Semiconductor Microelectronics, 51 IBM J. Res. & Dev. 605 (IBM 1997) and J. Chai, et al., Assembly of Aligned Linear Metallic Patterns on Silicon, 2 Nature Nanotechnology 500 (Nature Publishing Group 2007).
As techniques such as double patterning, spacer pitch doubling, and BCP self-assembly enable the creation of more closely spaced conductive lines, it becomes increasingly difficult to make an electrical connection to a particular line without overlapping and shorting between adjacent lines. Using traditional lithographic techniques, electrical connection pad sites also known as contact landing pads are too large to make contact with only a single conductive line in a group of closely spaced conductive lines. Present lithography technology does not have the resolution or alignment capability to print the patterns necessary to make connection sites for these smaller features. Thus, there exists a need for a technique to make electrical connections to closely spaced conductors and which may also be used to make electrical connections to any spaced apart parallel conductors.